CS25: Computer Architecture, Lab 3

Implementing an instruction set.

by Jeff Kaufman

In this lab I wrote a VHDL description for a simple processor, wrote an assembler for it and tested it by loading it onto a hardware simulation board.

The processor is built on the Harvard architecture, with separate data and program memories. This is useful because we can use RAM for the data but ROM for the program. It also allows us to save one bit on our addresses, as it is always clear from context whether an address is for data or for instruction. A two digit signed-hexadecimal output and an 8-bit DIP-switch input are also available to the processor. It has a reset button and a button to resume processing after a WAT ("wait") instruction. It has three addressing modes available: immediate, direct, and register indirect. Each opcode only has one addressing mode it can use. To provide full support for register indirect addressing I needed to add an SMQ ("store the ACC to the address in the MQ") instruction.

Processor Layout:

Register	Value	Size (bits)
WE	Write Enable	1
DMW	RAM input	8
DMF	RAM output	8
MBR	ROM output	10
ACC	Accumulator (main register)	8
MQ	Secondary register	8
MAR	Memory address register	5
PC	Program counter	5
DIP	The DIP switches	8
LED	Hexadecimal digit display	8
FLGS	Condition flags	2
BTN	Wakeup button	1

State Diagram:

Instruction	Meaning
Fetch1	Request the next instruction
Fetch2	Interpret the instruction
Wait1	If the button hasn't been pressed, stay here
AA1	Finish load direct
AB1	Set the RAM back to be read only
AC1	ADD the recieved operand to the accumulator
AC2	Clean up from the add, set flags appropriately
AD1	AND the recieved operand to the accumulator
DA1	Finish up the register indirect load
DB1	Finish up the register indirect save

Excecution Example:

To execute

   LIO
   ADD 00000

The processor goes through the following stages:

1.	Fetch1	: Bring down "LIO".
2.	Fetch2	: Set the ACC to the signal from the DIP.
3.	Fetch1	: Bring down "ADD 00000".
4.	Fetch2	: Set the MAR to "00000".
5.	AC1	: Add the contents of the DMF to the FatACC.
6.	AC2	: Set the ACC to a shrunken FatACC and set flags.

You can see it executing these steps in the simulator below:

simulator data

Implementing Memory and IO

I implemented both the RAM and ROM with Altera megafunctions. The RAM is 32 lines at 8 bits per line while the ROM is 10 bits per line. The RAM starts unassigned while the ROM is loaded from a MIF file.

The IO is mostly simple, connecting the DIPs through to the CPU. The display is a little more complicated, as converting the 8-bit output to the appropriate settings of the 15 segments requires many cases.

Assembler

The assembler takes in JSM files and writes out MIF files. It is written in java and will run as

"java AssemToo input.jsm
      ins_rom.mif"

. It supports variables, loops, pointers, and arrays.

Some example code:

C jAssem
int a,b; DEF a DEF b
a += b; LAD a ADD b STR a
a = 2; LDD 00000010 STR a
int c[4]; DEF c 3
for(int i = 0 ; i < 4 ; i++) c[i] = c[i] + b; DEF i LDD 00000000 STR i loop: LDD c ADD i SWP LMQ ADD b SMQ LDD 00000100 INV ADD i INV SWP JMQ loop

C	jAssem
`int a,b;`	`DEF a DEF b`
`a += b;`	`LAD a ADD b STR a`
`a = 2;`	`LDD 00000010 STR a`
`int c[4];`	`DEF c 3`
`for(int i = 0 ; i < 4 ; i++) c[i] = c[i] + b;`	`DEF i LDD 00000000 STR i loop: LDD c ADD i SWP LMQ ADD b SMQ LDD 00000100 INV ADD i INV SWP JMQ loop`

Jeff Kaufman : 2005
cbr at sccs dot swarthmore dot spam edu. Remove spam.

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